Alumini

Prof.Nisha Kuruvilla

Professor

ACADEMIC QUALIFICATIONS:  

  • Ph.D. in Electronics and Communication Engineering from the Centre for Nanotechnology Research, VIT University, Vellore, awarded in May 2013 for the thesis titled “Performance Analysis of Carbon Nanotubes for Futuristic IC Interconnects.

  • M.Tech in Electrical Engineering with specialization in Microelectronics and VLSI from the Indian Institute of Technology (IIT) Kanpur, completed in 2002.

  • B.E in Electronics Engineering from Marathawada University in 1990.

Work Experience

  •  32 years and 6 months of Teaching Experience. (Both for UG and PG students)
  •   1 year and 3 months of Industrial experience (HMT Kalamassery & Malayala Manorama)
  • Principal (i/c) – IHRD College of Engineering Kallooppara, Thiruvalla (January 2019 – August 2024)
  • Research Supervisor, APJ Abdul Kalam Technological University (APJAKTU), guiding doctoral research in VLSI, Nanoelectronics, and emerging semiconductor technologies
  • Member, Board of Studies (UG) – 2024 Scheme, APJ Abdul Kalam Technological University
  • Nominated University Representative, Academic Council Member, Saintgits College of Engineering (Autonomous), representing APJAKTU (2024–2027)
  • Nominated University Representative, Academic Council Member, Amal Jyothi College of Engineering (Autonomous), representing APJAKTU (2024–2027)
  • Coordinator, IHRD Career Advancement Scheme (CAS) Implementation Subcommittee, 2023–24
  • Chairperson, IHRD Committee for Drafting the Proposal for the IHRD Pension Scheme 2024, constituted by the Director, IHRD
  • Member, AICTE Expert Visit Committee – 2023
  • Member, Expert Visiting Committee, APJ Abdul Kalam Technological University (2015–16)
  • Academic Auditor, APJ Abdul Kalam Technological University
  • Head of the Department (Electronics), College of Engineering Chengannur – (May 2016 to May 2017), (September 2012 – November 2014), (2007–2010)
  • Placement Officer, College of Engineering Chengannur – (November 2014 to January 2019), (July 2010 to September 2013)
  • Founder & Advisor, IEEE SSCS Student Branch – College of Engineering Chengannur (2014–2019)
  • Founder & Advisor, IEEE SSCS Student Branch – College of Engineering Kallooppara (2022–2024)
  • PG Coordinator, College of Engineering Chengannur (June 2010 – June 2012)
  • Vice Chair, IEEE WIE Kerala Section (2010)
  • Branch Counselor, IEEE Student Branch, College of Engineering Chengannur (June 2004 – June 2007)
  • Secretary, Cooperative Society, College of Engineering Chengannur
  • Founder Secretary, ISTE Chapter, College of Engineering Chengannur (1998–2000)
  • Outstanding IEEE Student Branch Counselor International award for the academic year 2005-2006 by the Regional Activities Board and the Technical Activities Board of the IEEE.
  • Recipient Grurudarsanam Award 2014 by Sree Narayana Sevasamithi, in appreciation to the voluntary in engineering education.
  • Coordinator of DST funded type-0 project worth 80 Lakh rupees in College of Engineering Chengannur.(2012-2017)
  • Recipient of international student fellowship for participating and presenting paper in 14th Asia and South Pacific Design Automation Conference ASP-DAC 2009 held at Pacifico Yokohama, Yokohama, Japan under the Emerging Technologies and Applications topic.
  • Reviewer of IEEE Design & Test of Computers magazine.
  • Reviewer of Journal of Circuits, Systems and Computers by World Scientific Publishing.
  • Won Best paper award in International conference on computing, communication and signal processing- 2016.
  • Won Best paper award in 2 nd International Conference on Emerging Trends in Technology and Applied Science-2015
  • Instrumental in securing FIST Type 0 funded project from Department of Science and Technology -worth 83 Lakh rupees in College of Engineering Chengannur.(2012-2017) as Project coordinator.
  • Instrumental in securing a grant of $2000 from IEEE in 2004 as the IEEE Student Branch Counselor, for establishing a Center of Excellence Lab at College of Engineering Chengannur. The funding was based on a project proposal sanctioned in 2003, originally initiated by the 2003 IEEE Student Branch Counselor.
  • Instrumental in securing an award worth $500 from IEEE in 2004 for College of Engineering Chengannur, recognizing it as the Best Performing IEEE Women in Engineering (WiE) Affinity Group – 2004.
  • Sourced Annual Chapter Subsidy – IEEE SSCS- Instrumental in securing the Annual Chapter Subsidy of worth $8000 (@$2000 per year) from the IEEE Solid-State Circuits Society (SSCS) for the years 2016, 2018 & 2025 at College of Engineering Chengannur andfor the year 2023, at College of Engineering Kallooppara.

  Organizing and Coordinating Roles

  •   Organizing Chair, National Conference on Cyber Physical Systems (NCCPS 2024),held from 18/04/2024 to 20/04/2025, organized by College of Engineering Kallooppara with support from IEEE SSCS.
  •  Coordinator, National Workshop on “Advanced Nano-Scale Device Design Using TCAD”, conducted from 28/12/2015 to 01/01/2016 in association with IEEE SSCS.
  •  Coordinator, IHRD Faculty Development Programme on “Semiconductor Devices, Circuits and Systems – A Research Perspective”, from 04/07/2016 to 09/07/2016.
  •   Convener, Two-Day Workshop on “VLSI Design Automation”, held on 06/05/2016 and 07/05/2016.

International Conference Presentations

  • Presented a paper at IEEE ICM 2008, University of Sharjah, UAE.
  • Presented a paper under Emerging Technologies and Applications at IEEE ASP-DAC 2009, Pacifico Yokohama, Japan.

  Invited Keynote Addresses, Tutorials, and Expert Lectures 

  • “Enhancing Engineering Institution Visibility &Quality: A call for Action”, Mar Baselios Christian College of Engineering and Technology, Kuttikkanam
  • “Emerging Trends in Device Technology”, TKM College of Engineering.
  • “Empowering Women in Technology”, College of Engineering Adoor.
  • “Role of IEEE WIE in Shaping Professionalism”, NIT Calicut.
  • “VLSI Interconnects”, IEEE SSCS Chapter, Saintgits College of Engineering.
  • “The Role of CAD Tools in Research and Teaching”, IETE FDP, Saintgits College of Engineering.
  • “Emerging Devices in VLSI”, LBS Institute of Technology for Women.
  • “Emerging Technologies in VLSI”, Bishop Jerome Institute, Kollam.
  • “Emerging VLSI Interconnects”, STTP, College of Engineering, Karunagappally.
  • “VLSI Interconnects”, STTP on Recent Trends in VLSI and MEMS, Government Engineering College, Barton Hill, Thiruvananthapuram.
  • “Low Power VLSI”, ISTE STTP, Government Model Engineering College,Ernakulam.

Conference Chairing and Session Moderation

  • Chaired session on Microelectronics at the International Conference, Amal Jyothi College of Engineering, Kanjirappally.
  • Chaired session at the National Conference, Muslim Association College of Engineering, Venjaramoodu, Thiruvananthapuram.
  • Chaired session on Microelectronics at the International Conference, Government Engineering College (RIT), Kottayam.

International Journal Papers
1.   Anju Chakkikavil, Nisha Kuruvilla, Ayoob Khan, Shahul Hameed,” Structural Optimization of Wavy FinFET for Leakage Reduction and Performance Enhancement”, Advances in Science, Technology and Engineering Systems Journal Vol. 2, No. 3, 913-917 (2017)
2.   Nisha Kuruvilla, Sajeesh P T K, Shan N, “How To Brand An Engineering College From Rural Background – A Case Study”, IOSR-JRME   Volume-13-Issue-3, May – June 2023, DOI 10.9790/ 7388-1303011117
3.  Ravindran, A., George, A., Praveen, C. S., & Kuruvilla N. (2017). Gate All Around Nanowire TFET with  High ON/OFF Current Ratio. Materials Today: Proceedings, 4(9), 10637–10642. https://doi.org/10.1016/j.matpr.2017.06.434
4.  Nisha Kuruvilla and J. P. Raina. (2014 Impact of Bundle Structure on Performance of on-Chip CNT Interconnects. Hindawi Publishing Corporation Journal of Nanotechnology Volume 2014, Article ID 217519, 8 pages). https://dx.doi.org/10.1155/2014/217519
5.  Rahul Raj, Nisha Kuruvilla and Tintu K Thampi, “High Level Application Independent Optimum Voltage and Frequency Prediction for Low Power System” , International Journal of Computer Applications (0975 – 8887), pp 36-39, 2015
6.  Jyothi A, Nisha Kuruvilla, Ayoob Khan and Shahul Hameed T A Impact of Fin Shape on Fin FET Performance, International Journal of Computer Applications (0975 –8887) pp 1-4, 2015
7.  Sarojini S Potti , Dr. Sreelal S Pillai and Dr. Nisha Kuruvilla, “A Compact SPICE Model for Asymmetric Drain Spacer Extension FinFET” International Journal of ChemTech Research CODEN (USA): IJCRGG ISSN: 0974-4290 Vol.7, No.2, pp 842-849, 2014-2015
8.  Kollarama Subramanyam , Nisha Kuruvilla and J. P. Raina.(2014), Physical Parameter Based Compact Expression for Propagation Constant of SWCNT Interconnects World Academy of Science, Engineering and Technology, International Journal of Electrical, Electronic Science and Engineering Vol:8 No:1, pp139-143
9.  Antu Reeba Sam, Nisha Kuruvilla and J P Raina (2013), “Statistical Analysis of signal integrity issues in CNT interconnects due to contact resistance variations”, International Journal of Scientific &; Engineering Research,Volume 4, Issue 8, August 2013, ISSN 2229-5518
10.  Nisha Kuruvilla, Kollarama Subramanyam and J. P. Raina. (2012). Physical Parameter Based Model for Characteristic Impedance of SWCNT Interconnects and its Performance Analysis. IISTE Journal of Innovative System Design and Engineering 3(9),16-26. (IC Impact factor- 6.94)
11.  Nisha Kuruvilla, Amrutha S. R, J.P. Raina. (2012). Low-k Dielectric- A Potential Solution for Crosstalk Induced Signal Integrity issues in SWCNT Interconnects. IOSR Journal of VLSI and Signal Processing , 1 (1), 29-32.
12.  Nisha Kuruvilla, J P Raina, Arun Greig John and Athulya A, “Performance and Reliability Analysis of Bundled SWCNT as IC Interconnects”, Advanced Materials Research Vols. 129-131 (2010) pp 920-925,© (2010) Trans Tech Publications, Switzerland, doi:10.4028/www.scientific.net/AMR.129-131.920
13.  Nisha Kuruvilla, and J. P. Raina,” Carbon Nanotubes – A Solution for Tera Hertz’s IC Interconnect”, International Journal of Recent Trends in Engineering (Electrical & Electronics), Vol. 1, No. 4, June 2009, pp 32-36
14.  Arun Gerig John, Athulya A, Shnu Gervasis, Akhil G. Nair and Nisha Kuruvilla, “ A Performance Study of Carbon Nanotube Interconnects with CNT drivers: Comparison wit ITRS Predicted Drivers”, International Journal of Scientific Computing, Vol.3 , No.1 , January- June 2009, pp 155-160.
International Conference Papers
1.  Anu Sasindran and N. Kuruvilla;”Smoothened CNN-LSTM Hybrid Model with SpatioTemporal Attention Mechanism for River Water Level Prediction”; 2025 Emerging Technologies for Intelligent Systems (ETIS), Trivandrum, India, 2025, pp. 1-6, doi:10.1109/ETIS64005.2025.10961376.
2.  C. Anju; Nisha Kuruvilla; T. E. Ayoob Khan; T. A. Shahul Hameed, “Performance Analysis of Wavy FinFET and Optimization for Leakage Reduction”, 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) 2016, pp 83-88, DOI: 10.1109/iNIS.2016.030
3.  Vani R and Nisha Kuruvilla ,” 3D TCAD based parasitic capacitance extraction and frequency response analysis in multigate devices”, International conference on computing, communication and signal processing, July 8 th to 9 th 2016, organized by College of engineering, Karunagappally,pp 414-418 (Won Best Paper Award )
4.  Anju C and Nisha Kuruvilla ,” Optimized wavy FinFET- A solution for high performance low power device”, International conference on computing, communication and signal processing, July 8 th to 9 th 2016, organized by College of engineering, Karunagappally,pp 419-424
5.  Antu Reeba Sam , Nisha Kuruvilla and Sarojini S Potti, “Compact Equivalent single conductor model for MWCNT Interconnect” , IEEESSCS sponsored 4 th conference solid state circuits , 25 th and 26 th August 2016, pp170-175
6.  Jyothi A, Nisha Kuruvilla, Ayoob Khan and Shahul Hameed T A Impact of Fin Shape on Fin FET Performance, 2 nd International Conference on Emerging Trends in Technology and Applied Science, SAINTGITS College of Engineering, Kottayam, Kerala, India, 3oth April -2d May 2015 (Won Best Paper Award )
7.  Jesty Bhaskar and Nisha Kuruvilla, “Performance Analysis of Low Power Data Retentive Volatile Memory , 2 nd International Conference on Emerging Trends in Technology and Applied Science, SAINTGITS College of Engineering, Kottayam, Kerala, India, 3oth April -2d May 2015
8.  Rahul Raj, Nisha Kuruvilla and Tintu K Thampi, “High Level Application Independent Optimum Voltage and Frequency Prediction for Low Power System” , 2nd International Conference on Emerging Trends in Technology and Applied Science, SAINTGITS College of Engineering, Kottayam, Kerala, India, 3oth April -2 nd May 2015
9.  Sarojini S Potti , Dr. Sreelal S Pillai and Dr. Nisha Kuruvillla, “A Compact SPICE Model for Asymmetric Drain Spacer Extension FinFET”, ICONN 2015 [4th -6th Feb 2015] International Conference on Nanoscience and  Nanotechnology-2015 SRM University, Chennai, India
10.  Nisha Kuruvilla, Anilkumar C V, “Performance Analysis of Carbon Nanotube Interconnects -A Statistical Approach”, ICVLSI 2008, Feb. 14-16, 2008, pp 163- 168 ,Organized by Velammal engineering College, Chennai.
11.  Nisha Kuruvilla, Saju Thomas, Joseph John, “Studies on point to point optical wireless links”, International conference on wireless communication networks, June 27-29, 2003, organized by SSN Engineering College, Chennai.
12.   Nisha Kuruvilla, J P Raina and Arun Gerig John, “Performance and reliability analysis of Mixed CNT bundle vs SWCNT Bundle as IC Interconnects, International Conference on “Carbon Nanotechnology: Potential and Challenges”, December 15-17, 2010, organized by Advanced Nanoengineering Materials Laboratory Department of
Mechanical Engineering and Materials Science Programme Indian Institute of Technology Kanpur (IITK), Kanpur, (UP) India in association with Indian Society for Advancement of Materials and Process Engineering, pp 26-37
13.  Nisha Kuruvilla and J.P.Raina, “Carbon Nanotube IC Interconnects of various geometries – A Performance Analysis”, Poster present in International Symposium on nanotechnology Present &Future Trends, organized by Center of Nanotechnology research, VIT University, Vellore, August 25 th &26 th , 2010.
14.  Nisha Kuruvilla, J P Raina, Arun Greig John and Athulya A, “Performance and Reliability Analysis of Bundled SWCNT as IC Interconnects”, ICMMT 2010, September 17-19, 2010, Chongqing, China
15.  Nisha Kuruvilla, J P Raina and Arun Gerig John, ““A Comparative Analysis of Process Fluctuations Induced Parasitic Variations of Mixed CNT vs SWCNT Bundle Interconnects”, ICNB 2010,International Conference on Nanotechnology and Biosensors, Jan. 20-21, 2010, pp 12, Organized by IACQER
16.  Nisha Kuruvilla and J.P.Raina “Statistical Sensitivity Analysis of Latency of Carbon
Nanotube Interconnects due to Contact Resistance Variations”, IEEE ICM 2008, 20th International Conference on Microelectronics December 14 th -17 th 2008, University of Sharjah. pp 340-343.
17.  Nisha Kuruvilla and J.P.Raina “Performance Analysis of Carbon Chips”, Poster present in 14th Asia and South Pacific Design Automation Conference ASP-DAC 2009, IEICE VLD Student Forum Poster Presentation, Jan. 19-22, 2009 at Pacifico Yokohama, Yokohama, Japan under the Emerging Technologies and Applications topic.
18.  Antu Reeba Sam, Nisha Kuruvilla and J P Raina “Statistical Analysis of signal integrity issues in CNT  interconnects due to contact resistance variations”, ICGITS 2013, Saint Gits, Kottayam, 04.04.13-06.04.13
19.  Tintu K Thampy, Nisha kuruvilla and Lisa Mathew,” An Optimized Architectural Level Leakage Aware Power Estimator using DVS”, ICCEECON2k15, Christ Knowledge City
National Conference Papers
1.  Anu Sasindran and N. Kuruvilla, ;Rainfall Prediction: A comparative study of stacked LSTM, BiLSTM and GRU deep learning models for Univariate Timeseries Forcasting&, National Conference on Cyber Physical Systems NCCPS 2024, 18/04/2024 – 20/04/2025
2.  Abdul Hakeem and Nisha Kuruvilla,” RF Parameter Extraction and Performance Analysis of Different Types of nanowire MOSFETs”, 3 rd National Conference of the Emerging trends in VLSI, Embedded Systems, opto electronics and Signal Processing , organized by Model Engg. College , May 14-16 2015
3.  Amrutha S R,Nisha Kuruvilla and J P Raina, ' Crosstalk Induced Signal Integrity Issues in various CNT Interconnect Geometries', in the presentation of the 4th National Conference on Signal Processing, Communications and VLSI Design organized by Dept. ECE of Anna University of Technology, Coimbatore on 9th
June 2012.
4.  Jain P Uthup and Nisha Kuruvilla “Performance Comparison of the logic devices using Silicon and CNT technology for deep submicron ICs” in the presentation of the 4th National Conference on Signal Processing,
Communications and VLSI Design organized by Dept. ECE of Anna University of Technology, Coimbatore on 9th june 2012.
5.   Nisha Kuruvilla, J.P. Raina. Anilkumar C V, ”Load Depended Performance Analysis of SWCNT as VLSI Interconnects”, National conference on VLSI and communication -2008 (NC-VCom 2008), Organized by SAINGITS College of Engineering, Mar 14 th -15 th , 2008 pp 141-144.
6.  Nisha Kuruvilla, Liza Mathew, “Wire width planning for Zero Skew Routing in High Speed VLSI L Layouts”, National Conference on Microelectronics and Communication, SRM University, Tamil Nadu Aug. 24-27, 2007.
7.  Nisha Kuruvilla, Joseph John, “Studies on IrDA Compatible Links for High Speed Indoor Data Transmission”, National Conference on Communication Networking (NCCN 2003), SRM Engineering College, Tamil Nadu Feb. 26-28,2003.

Courses Taught
Postgraduate (PG) Level

  •     Electronic Design Automation (EDA) Tools
  •     VLSI Design
  •     Low Power VLSI
  •     Physical Design Lab

Undergraduate (UG) Level

  •   VLSI Design
  •   ASIC Design
  •   Solid State Electronics
  •   Digital Electronics
  •    Electronic Circuits
  •    Microprocessors
  •    Advanced Microprocessors
  •    Test and Measuring Instruments
  •    Linear Integrated Circuits

 Research Interests

  •  Climate Studies (AI-based modelling and prediction)
  •  Modelling and Performance Analysis of Emerging Devices in VLSI
  •  Carbon Nanotube (CNT) Interconnects for future IC technologies
  •  Low-Power VLSI Design
  •  Design and Optimization of VLSI Interconnects
  •  Digital VLSI Systems
  • Solid State Electronics and Device Physics